Single-phase transformerless nine-level inverter with voltage boosting ability for PV fed AC microgrid applications

This letter presents a new single-stage common ground type nine-level (9L) switched-capacitor inverter topology with single-phase operation. The primary objective of this topology is to reduce the leakage current, voltage boosting, and maintain the voltage across the switched capacitors. The output voltage (vo) can be boosted up to two times the input voltage (vin). The various modes of operations are explained in detail, and the simulation results are provided to illustrate the effectiveness of the proposed topology. Next, the experimental results are obtained from a 500 W prototype setup and tested under different scenarios such as load variations, input voltage, and modulation index. Both simulation and experimental results have a good agreement regarding efficiency and performance. Finally, a detailed comparative study is performed with other recent 9L switched-capacitor inverters to prove the merits of the proposed topology.

www.nature.com/scientificreports/ not have voltage gain, and the number of ON state switches is high at each level. Moreover, this topology's input voltage requirement is significantly higher due to reduced dc-bus utilization. Another novel 9L-TLI topology is proposed in 13 , which has full dc-bus utilization. The buck-boost converters are integrated with a series connection of four dc-link capacitors to achieve the nine-level output voltage. However, the dc-link capacitors are not balanced, leading to unsymmetrical stepped waveforms at the load. In this reference, it may be noted that the common connection between the load side ground terminal and the source side negative terminal eliminates the leakage current and is called the common ground connection 14 . Recent 9L SCMLI topologies with boosting are presented in [15][16][17] . However, they fail to reduce leakage current. Moreover, the topologies presented in [18][19][20] share a common ground with eradicating leakage current. The 18 presents a new common ground in the three-level inverter. The capacitor acts as a virtual dc source in the negative half cycle. If the capacitor fails, the topology will not generate the negative half cycle, and the entire system will fail. However, if any capacitor fails in the proposed topology, the magnitude of the output voltage and step size will be reduced, but the operation will continue. Motivated by the above discussion, this paper presents a new common ground type (CGT) inverter with a reduced total power component. The proposed topology is an improved version of 10 . The proposed topology successfully reduces the number of power components, achieving a low voltage rating of FCs and low power loss with a maximum of ~ 97.2% of efficiency. It is important to note that the proposed topology reduces leakage current due to common grounding, which is missing in the existing 9L SCMLI inverter topologies 2-13 .

Proposed TL-9L inverter topology
Description of proposed topology. A detailed explanation of the circuit diagram and the modes of operations are discussed for the proposed TL-9L inverter. A detailed explanation of the circuit diagram and the modes of operations are discussed for the proposed CGT-T9L inverter. Figure 1 shows the circuit diagram of the proposed 9L inverter topology. It can be observed from Fig. 1 that it has a single dc source with three FCs (C 1 , C 2 , and C 3 ) rated at voltage v in /2 (C 2 , and C 3 ) and v in , (C 1 ). The proposed topology uses ten switches (S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 7 , S 8 , S 9 , and S 10 ) and three diodes (D 1 , D 2 , and D a ). The capacitor C 1 is connected in such a way that it gets charged when S 1 is turned ON. The series-connected capacitors C 2 and C 3 are connected with switches S 7 , S 8, and S 9 /S 10 . The switch pairs S 7 , and S 8 should not be turned ON simultaneously to avoid the short circuit of the series-connected capacitor branch. Likewise, the switch pairs (S 1 , S 2 ), (S 3 , S 6 , S 4 ), and (S 3 , S 5 , S 4 ) should not be turned ON simultaneously. The midpoint of C 2 and C 3 is connected with S 9 and S 10 . It may be observed that the switches S 7 , S 8, and S 9 /S 10 form a T-type leg which also serves as one of the terminals of the load, i.e., node a. The load terminal is directly connected to the negative terminal of the dc source i.e., node n. Figure 2a-i shows the sub-circuit diagram of the various modes of operation, showing the path of the charging current and load current. The capacitor C 1 gets charged in all the positive levels and the first level of the negative half cycle. A few modes are explained below to understand the working principle of the whole topology.

Modes of operation with pulse generation scheme.
In Fig. 2, three different color lines are shown, which illustrate the current path of the proposed circuit diagram during (1) the charging of the capacitors, (2) the current path for unity power factor, and (3) the current path in either lagging or leading power factor.
Mode + v in /2 In this mode, the FC C1 and the series-connected capacitor branch (C 2 and C 3 ) are charged simultaneously up to the v in . The switch S 9 /S 10 is turned ON and the load voltage is equal to + v in /2, as shown in Fig. 2a.
• T h e c l o s e d p a t h f o r c h a r g i n g C 1 -C 3 i s s h o w n a s : In this mode, all the FCs charge simultaneously, and the load voltage equals + v in, as shown in Fig. 2b.
Mode + 3v in /2 In this mode, FC C 3 discharges, but FC C 1 charges. The load voltage is equal to + 3 v in /2, as shown in Fig. 2c.
• The closed current path for charging of C 1 is shown as: v in →↑ C 1 → D a → v in • The closed current path for load is shown as: v in → S 1 → S 3 ↓ C 3 → S 9 S 10 → v in Mode + 2v in In this mode, the FC C 2 and C 3 get discharged, and the load voltage is equal to + 2 v in, as shown in Fig. 2d.
• The closed current path for charging of C 1 is shown as: Mode + 0v in During this mode, all the FCs are charging, and the load voltage is equal to + 0 v in, as shown in Fig. 2e.
The explanation of the various modes for the negative half cycle is similar, and the corresponding turned-on switches for each voltage level and charging and discharging state of the capacitors are given in Table 1. Further, as shown in Fig. 2, the proposed topology can operate in both real and reactive power. The conventional levelshifted SPWM (LSPWM), as shown in Fig. 3a, and the PWM logic functions, as shown in Fig. 3b, are used in the proposed topology to generate the 9L output voltage. The reference voltage (V ref ) is compared with the triangular carrier waveform (Carr 1-Carr 8) and produces the pulses. The simple logic functions are used to generate the desired pulses for the switches. Since the maximum output voltage of the proposed inverter is two times higher than the v in, it generates the 9L stepped voltage waveform with each step of v in /2.

Determination of capacitance and power analysis.
Determination of capacitance. The proposed topology employs three capacitors, labeled C 1 , C 2 , and C 3 . These capacitors play a vital role in boosting the input voltage. Thus, the output voltage is equal to 2 v in , and each step has a voltage of v in /2. The switching capacitor C 1 is charged to its maximum input voltage, while the flying capacitors C 2 and C 3 are charged to 50% of the input www.nature.com/scientificreports/ voltage. Consequently, the capacitance value selection of these capacitors is more critical to achieving the 9L output voltage. In addition, it affects the inverter's ripple loss, size, and total cost. As seen in Fig. 3a, the switched capacitor C 1 's capacitance value was calculated using the longest discharging time of capacitors. The capacitances are estimated by using a maximum of 10% capacitor ripple voltage. The capacitor C 1 is discharged during all the negative levels (− 0.5 v in , − v in , − 1.5 v in , − 2 v in ) as shown in Fig. 3a. The time duration t is estimated as follows,where 2π is the output voltage waveform's period. The predicted charge on the capacitor C1 under resistive load for the LDC period is: The current load value of the proposed topology for the purely resistive load can be expressed as, From Eqs. (3) and (4), the charge on the capacitor C 1 is estimated as, The optimal capacitance value of capacitors C 1 when the load is entirely resistive may be calculated as follows: θ 1 = π/10, θ 2 =π/5, θ 3 = 6π/20, θ 4 = 2π/5, θ 5 = π/2, θ 6 = 6π/10, θ 7 = 7π/10, θ 8 = 4π/5, θ 9 = 9π/10 S1, S3, S6, S9, S10, Da ▲ ▲ ▲ +3vin/2 C S1, S3, D1, D2, Da, S4, S7 ▲ -▼ +vin D S1, S3, D1, D2, Da, S4, S9, S10 ▲ ▼ ▼ +vin/2 O S1, S3, D1, D2, Da, S4, S8 ▲ ▲ ▲ 0 vin A' S1, S5, S4, S9, S10, Da At resistive-inductive (RL) loading conditions, the charge on capacitor C 1 is approximated as follows: The optimal capacitance value of capacitors C 1 under resistive-inductive (RL) loading may be calculated as follows: The size of flying capacitors C 2 and C 3 are estimated as, where I mx is the maximum load current, f s is the switching frequency, and ΔV C is the voltage ripple.
Power loss analysis. Switching, conduction, driver circuit, and ripple loss are used to compute inverter power loss 19 . IGBT switching loss occurs when its anti-parallel diode is off (9) Switching loss during the IGBT is OFF, and Diode is ON as expressed in (10) The conduction losses are always high due to the long conduction period, and this can be calculated by using (11) where 'V CE ' is the collector and emitter voltage of IGBT, i.e. blocking voltage, 'V F ' forward voltage of the diode, 'I o ' is the load current, and 't r ' rise time, t d(ON) and t d(OFF) is turn ON, and OFFF delay and 't f ' is fall time of an IGBT. 'R CE(on) ' is the on-state resistance of an IGBT, 'd' is the duty cycle of the IGBT, and 'T s ' is the switching period.
Further, the gate driver loss is very small and negligible. However, the calculation of the gate driver loss is given in (12) where the 'Q B ' is charge at the base terminal, 'V BE ' biasing voltage to the IGBTs , and f s switching frequency. The energy loss across the capacitor during the charging is expressed as E Cap = 1 2 C × (�V ) 2 . C 2 and C 3 charge twice per half-cycle, whereas C 1 charges four times. Average capacitor cycle loss is E Rip = 2f o (E Cap ) . Thus, the total across the capacitors in the complete cycle is

Results and discussion
The performance of the proposed topology is validated in MATLAB / Simulink software tool and a laboratorybuilt hardware prototype. The input DC source voltage is kept at 100 V. The voltage and capacitance value of FC C 1 is respectively 100 V and 2700 µF. Similarly, the voltage and capacitance values of FCs C 2 and C 3 are 50 V/2700 µF, respectively. The capacitance values are designed per the process given in 14 , where the maximum voltage ripple is chosen as less than 5% with a 2.5 kHz switching frequency. The two resistive-inductive loads are used with R = 100 Ω, L = 50 mH, and R = 50 Ω, L = 100 mH. The output voltage and current waveform with these two loads are given in Fig. 4a. The corresponding capacitor ripple voltage is given in Fig. 4b for C 2 and C 3 and Fig. 4c for C 1 . Further, the simulation result of each FCs current is shown in Fig. 5a-d, and the loop inductor current is shown in Fig. 5d.
For experimental validation for 500 W prototype model was rigged up with the DC Source taken from a three-phase rectifier (600 V, 100A), the capacitors C 1 -2200 µF/100 V (ALS30A222DA100) and C 2 , C 3 -1700 µF/50 V (SLPX332M050C1P3). A little higher value of capacitance is chosen due to practical considerations like suppressing the effect of unnecessary parasitic wiring inductance. Here, the power electronics devices are chosen as IGBTs (600 V, 73 A) SKM75GB63D from Semikron. The diode (200 V, 30 A) HER3003 from DC Components is used where only a single diode is used in the proposed topology as given in Table 2. A notable drawback of the switched capacitor circuits is the high inrush current. In this paper, a current limiting inductor is used to reduce the inrush current. The inductor size is small and can limit the inrush current to an allowable value 14 . The mathematical expression for the current limiting inductor is given in (13).    where the i l,in is the maximum inrush current or loop current during the charging of the FCs. L in is inductance value and C f is FC capacitance value. i c is charging current i.e. FC current which is usually four to five times higher than the load current. For the suppression of inrush current the loop inductor value is chosen as ~ 20 A for L l,in = 40 μH based on (1). The experimentally obtained output voltage and current waveforms for R = 50 Ω, L = 100 mH (peak current (I peak ) = ∼ 3.3 A) with power factor of 0.85 and R = 100 Ω, L = 50 mH (I peak = ∼ 1.9 A) with power factor of 0.99 is presented in Fig. 6a,b, respectively, and they confirm that the peak of the output voltage is 200 V which is two times higher than the input voltage. Most of the loads are dynamic behavior, so it is necessary to evaluate the proposed topology for different loading condition. Figure 7a shows the continuous load change from R = 100 Ω to 55 Ω with constant L = 50 mH, and in Fig. 7b, the capacitor current for load change is presented. As explained earlier, in SCMLI topologies, the inrush current is a big challenge addressed in the proposed topology using the loop inductor. The current flowing through the FCs is presented in Fig. 7b.
It can be observed from Fig. 7b that the inrush current or the FC current is significantly reduced in the proposed topology but the inrush current is a little higher than the calculated value. However, the inductor (L in ) reduced the maximum inrush current four times less than the without inductor current. In order to show the performance of the proposed topology during modulation, index variations are tested, and the corresponding waveform is shown in Fig. 8. Further, the various experimental results for step input change (80-100 V) with FCs voltages are shown in Fig. 9. The blocking voltage and current of switches (S 3 and S 4 ) as shown in Fig. 10a, and capacitor voltage for load changing is presented in Fig. 10b. The voltage stress on the switches is equal to the v in , whereas other topologies presented in Table 3 show the voltage stress is two and four times higher than the v in . Most of the SCMLI topology with boosting ability circuits have higher current stress than the conventional inverter. It can be limited by inserting the small inductor in the capacitor charging path, but it is worth mentioning that the voltage boosting ability without any additional circuit is achieved. The comparison of the proposed TL-9L inverter topology with other recent 9L SCMLIs is presented in Table 3. It can be observed that the number of power components count is considerably low in the TL-9L inverter. However, it may also be observed from Table 2 that a few existing topologies have fewer switches compared to the proposed topology.
However, the proposed topology is addressed the leakage current problem entirely as it is of common ground type and these features are not available in any other 9L inverters presented in the given literature. Apart from this, the proposed topology can address the inrush current issue despite being a boost-capable switched capacitor type. It may be noted that none of the existing switched capacitor type 9L inverters [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17]19,20 have this advantage. The power loss breakdown of the individual components of the proposed topology is given in Fig. 11a. Due to the charging current, the losses are high in FCs and the IGBTs carrying the charging current. The simulation efficiency of the proposed topology is 97.4%, with a total loss of 13 W for ~ 500 W output power. However, in the experimental setup, the measured efficiency is ~ 95.8% for the unity power factor, as shown in Fig. 11b, with an approximate total power loss of ~ 21 W. The experimental efficiency is measured using the Fluke 434-II power quality meter. The photo of the scaled-down experiment setup is shown in Fig. 11c.

Conclusion
This paper has presented a new TL-9L inverter topology width that reduced the total number of power components. The discussion confirms that the proposed topology requires a lower number of power components. The performance of the proposed topology is analyzed in both simulation and scaled experimental setup.

Data availability
The datasets analyzed during the current study are available from the corresponding author on reasonable request.